Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36525 )
Change subject: intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER ......................................................................
intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER
Note that due to UNKNOWN_TSC_RATE, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the cpu.
Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/slot_1/Kconfig M src/northbridge/intel/i440bx/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 3d0522a..10001bd 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,7 +24,8 @@ select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX select NO_SMM - select NO_MONOTONIC_TIMER + select UDELAY_TSC + select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE
config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 45cdd9c..df1e365 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,7 +17,6 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select UDELAY_IO
config SDRAMPWR_4DIMM bool