7 Jan
2021
7 Jan
'21
9:37 a.m.
Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/a6ea399a_82656bfa PS2, Line 18: /* TODO check how to determine CPU PCIE port */
Yes, I asked Subrata, but no respond.. sad. […]
Verified this, it's:
bit 0 = 00:06.0 bit 1 = 00:01.0 bit 2 = 00:06.2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Gerrit-Change-Number: 49021
Gerrit-PatchSet: 2
Gerrit-Owner: EricR Lai ericr_lai@compal.corp-partner.google.com
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Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
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