[coreboot-gerrit] Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5

[Subrata Banik (Code Review)]

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sridhar Siricilla, Arthur Heymans, Nick Vaccaro, Eric Lai, Felix Held.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 )

Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
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Patch Set 6:

(1 comment)

Patchset:

PS6:
> Can the reset be just called on the resume from S5 path instead of in the smihandler before entering S5?

Could be done, but I prefer resetting the controller during entry path instead resume.

1. At resume we have to reset the XHCI controller early, don't know if there is any complication of XHCI being pursued it's bad state while it entered into S5 and upon resume also, the state is remain the same, unless reset explicitly. 
2. Doing early XHCI reset, meaning, keeping this code into the bootblock (which is typically, RO for Chrome FW), hence, we wish to keep it outside RO.
3. If Intel could figure out any better solution to fix this problem then we can revert the SMI handler W/A easily.