Hello Patrick Rudolph, Arthur Heymans, Matt DeVillier,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/libgfxinit/+/32732
to look at the new patch set (#2).
Change subject: dp training: Write correct training data when switching patterns ......................................................................
dp training: Write correct training data when switching patterns
Apparently this was wrong all the time. When switching the training pattern, i.e. writes to DPCD+0x102, we also have to write the current signal levels to subsequent offsets. We always wrote 0s in this case, even if we already negotiated higher values during the clock-recovery phase. Obviously, this results in havoc if the sink takes the 0s serious.
TEST=Run a few hundred training rounds with a Terra 2462W display. This display almost always requested an increase of the voltage swing to level 1. Trainings where it recovered the clock with level 0 always succeeded, while trainings with level 1 almost always lost synchronization at the start of channel equalization. With the patch applied, all trainings succeeded.
Change-Id: I6ae2f9aaec0b042e8dee6e8b0099ea62c82f611b Signed-off-by: Nico Huber nico.huber@secunet.com --- M common/hw-gfx-dp_training.adb 1 file changed, 11 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/32/32732/2