[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: pass MMCONF base address to FSP via UPD

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50239 )

Change subject: soc/amd/cezanne: pass MMCONF base address to FSP via UPD
......................................................................

soc/amd/cezanne: pass MMCONF base address to FSP via UPD

Signed-off-by: Felix Held 
Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee
---
M src/soc/amd/cezanne/romstage.c
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/50239/1

diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index f790def..0d0e953 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -8,6 +8,9 @@

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
+	FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
+
+	mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
 }

asmlinkage void car_stage_entry(void)
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
index 338133c..89f5fc7 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -12,6 +12,7 @@
 /** Fsp M Configuration
 **/
 typedef struct __packed {
+	/** Offset 0x0040**/	uint32_t                    pci_express_base_addr;
    uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;