Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32907 )
Change subject: [WIP] Documentation: How to run coreboot on PC Engines apu1 ......................................................................
Patch Set 1:
(4 comments)
You may also add a link to the open schematics on PC Engines site. It would look great
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu1.md:
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 13: | Boot | From SD card, USB, m-SATA | mSATA, SATA
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 25: | Write protection | no | available with jumper on #WP pin?
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 34: `flashrom -p internal -c MX25L1606E -w coreboot.rom `
Please remove the `…` and indent it with four spaces.
should also be "MX25L1606E", flashrom expects the chip to be passed in quotes ""
https://review.coreboot.org/#/c/32907/1/Documentation/mainboard/pcengines/ap... PS1, Line 39: ACPI : Specification documentation
Add a link?
Add information that S5 can be forced by shorting power button pin on J2 header.