Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3809
-gerrit
commit fd309f94cf85cf910910420b23157bc40094901b Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Jul 26 08:35:09 2013 +0300
intel/i82801ix: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO.
Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/southbridge/intel/i82801ix/hdaudio.c | 24 ++++++++++-------------- src/southbridge/intel/i82801ix/i82801ix.c | 22 +++++++++------------- src/southbridge/intel/i82801ix/pcie.c | 14 +++++--------- src/southbridge/intel/i82801ix/smihandler.c | 6 +++--- 4 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 2d75d11..d950596 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -237,39 +237,35 @@ static void azalia_init(struct device *dev) u8 reg8; u32 reg32;
-#if CONFIG_MMCONF_SUPPORT // ESD - reg32 = pci_mmio_read_config32(dev, 0x134); + reg32 = pci_read_config32(dev, 0x134); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x134, reg32); + pci_write_config32(dev, 0x134, reg32);
// Link1 description - reg32 = pci_mmio_read_config32(dev, 0x140); + reg32 = pci_read_config32(dev, 0x140); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x140, reg32); + pci_write_config32(dev, 0x140, reg32);
// Port VC0 Resource Control Register - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32);
// VCi traffic class - reg8 = pci_mmio_read_config8(dev, 0x44); + reg8 = pci_read_config8(dev, 0x44); reg8 |= (7 << 0); // TC7 - pci_mmio_write_config8(dev, 0x44, reg8); + pci_write_config8(dev, 0x44, reg8);
// VCi Resource Control - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); reg32 |= (1 << 24); // VCi ID reg32 |= (0x80 << 0); // VCi map - pci_mmio_write_config32(dev, 0x120, reg32); -#else -#error ICH9 Azalia required CONFIG_MMCONF_SUPPORT -#endif + pci_write_config32(dev, 0x120, reg32);
/* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index e35487f..0fe7d20 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -27,6 +27,10 @@ #include <console/console.h> #include "i82801ix.h"
+#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#error ICH9 requires CONFIG_MMCONF_SUPPORT_DEFAULT +#endif + typedef struct southbridge_intel_i82801ix_config config_t;
static void i82801ix_enable_device(device_t dev) @@ -66,13 +70,9 @@ static void i82801ix_pcie_init(const config_t *const info) printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); } -#if CONFIG_MMCONF_SUPPORT - reg32 = pci_mmio_read_config32(pciePort[i], 0x300); - pci_mmio_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); - pci_mmio_write_config8(pciePort[i], 0x324, 0x40); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + reg32 = pci_read_config32(pciePort[i], 0x300); + pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_write_config8(pciePort[i], 0x324, 0x40); }
if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { @@ -87,13 +87,9 @@ static void i82801ix_pcie_init(const config_t *const info)
for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { /* Only for the top disabled ports. */ -#if CONFIG_MMCONF_SUPPORT - reg32 = pci_mmio_read_config32(pciePort[i], 0x300); + reg32 = pci_read_config32(pciePort[i], 0x300); reg32 |= 0x3 << 16; - pci_mmio_write_config32(pciePort[i], 0x300, reg32); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + pci_write_config32(pciePort[i], 0x300, reg32); }
/* Set slot implemented, slot number and slot power limits. */ diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index ce5d265..f53519d 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -56,23 +56,19 @@ static void pci_init(struct device *dev) reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); pci_write_config32(dev, 0xe1, reg32);
-#if CONFIG_MMCONF_SUPPORT /* Set VC0 transaction class */ - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32);
/* Mask completion timeouts */ - reg32 = pci_mmio_read_config32(dev, 0x148); + reg32 = pci_read_config32(dev, 0x148); reg32 |= (1 << 14); - pci_mmio_write_config32(dev, 0x148, reg32); + pci_write_config32(dev, 0x148, reg32);
/* Lock R/WO Correctable Error Mask. */ - pci_mmio_write_config32(dev, 0x154, pci_mmio_read_config32(dev, 0x154)); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154));
/* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 5b6eafa..6d17621 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -344,7 +344,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl;
- bios_cntl = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -358,7 +358,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_mmio_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -501,7 +501,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u32 smi_sts;
/* Update global variable pmbase */ - pmbase = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc;
/* We need to clear the SMI status registers, or we won't see what's * happening in the following calls.