[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb700/bootblock.c: Add post codes to LPC or PCI configuration

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62106 )

Change subject: sb/amd/sb700/bootblock.c: Add post codes to LPC or PCI configuration
......................................................................

sb/amd/sb700/bootblock.c: Add post codes to LPC or PCI configuration

The code is copied without modification from 4.11_branch
src/southbridge/amd/sb700/early_setup.c file. Add it to the bootblock
southbridge init.

Signed-off-by: Michał Żygowski 
Change-Id: I8c700dfcc0811d97322213dcd6d41a2267006f3d
---
M src/southbridge/amd/sb700/bootblock.c
1 file changed, 69 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/62106/1

diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index bacf7a8..dbd25f5 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -128,9 +128,78 @@
    pci_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
 }

+static void sb7xx_51xx_pci_port80(void)
+{
+	u8 byte;
+	pci_devfn_t dev;
+
+	/* P2P Bridge */
+	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
+
+	/* Chip Control: Enable subtractive decoding */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 5;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 7;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* The same IO Base and IO Limit here is meaningful because we set the
+	 * bridge to be subtractive. During early setup stage, we have to make
+	 * sure that data can go through port 0x80.
+	 */
+	/* IO Base: 0xf000 */
+	byte = pci_read_config8(dev, 0x1C);
+	byte |= 0xF << 4;
+	pci_write_config8(dev, 0x1C, byte);
+
+	/* IO Limit: 0xf000 */
+	byte = pci_read_config8(dev, 0x1D);
+	byte |= 0xF << 4;
+	pci_write_config8(dev, 0x1D, byte);
+
+	/* PCI Command: Enable IO response */
+	byte = pci_read_config8(dev, 0x04);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x04, byte);
+
+	/* LPC controller */
+	dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
+
+	byte = pci_read_config8(dev, 0x4A);
+	byte &= ~(1 << 5);	/* disable lpc port 80 */
+	pci_write_config8(dev, 0x4A, byte);
+}
+
+static void sb7xx_51xx_lpc_port80(void)
+{
+	u8 byte;
+	pci_devfn_t dev;
+	u32 reg32;
+
+	/* Enable LPC controller */
+	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
+	reg32 = pci_read_config32(dev, 0x64);
+	reg32 |= 0x00100000;	/* lpcEnable */
+	pci_write_config32(dev, 0x64, reg32);
+
+	/* Enable port 80 LPC decode in pci function 3 configuration space. */
+	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);
+	byte = pci_read_config8(dev, 0x4a);
+	byte |= 1 << 5;		/* enable port 80 */
+	pci_write_config8(dev, 0x4a, byte);
+}
+
 void bootblock_early_southbridge_init(void)
 {
    sb700_enable_rom();
    sb700_configure_rom();
    sb700_enable_io_decodes();
+
+	if (CONFIG(POST_DEVICE_LPC))
+		sb7xx_51xx_lpc_port80();
+	if (CONFIG(POST_DEVICE_PCI_PCIE))
+		sb7xx_51xx_pci_port80();
 }