13 Nov
2019
13 Nov
'19
4:11 p.m.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36812 )
Change subject: AGESA,binaryPI: Move SCI enable outside table creation ......................................................................
Patch Set 1:
If I understand correctly, clearing a SCI is AMD dependent? Intel silicon is free of this flaw?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I37810771090dd9b0377f9a72c7a17ef1564ccf68
Gerrit-Change-Number: 36812
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-CC: Michał Żygowski michal.zygowski@3mdeb.com
Gerrit-Comment-Date: Wed, 13 Nov 2019 16:11:32 +0000
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