Attention is currently required from: Philipp Hug, ron minnich.
Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76689?usp=email )
Change subject: soc/sifive/fu740: Add FU740 SOC ......................................................................
Patch Set 11:
(6 comments)
File src/soc/sifive/fu740/Kconfig:
https://review.coreboot.org/c/coreboot/+/76689/comment/ed1f3a7f_1e840330 : PS10, Line 28: # working HART uses U7 core
RISCV_WORKING_HARTID is set to 0, which is S7?
Done
https://review.coreboot.org/c/coreboot/+/76689/comment/89539ec6_9644bdc9 : PS10, Line 47: default 0 # use S7 core as default hart
deliberate use of S7 for coreboot?
Oh that is not correct. I have to use U7, because S7 does not have supervisor mode support. Not a problem using OpenSBI, but still. Changed it.
File src/soc/sifive/fu740/clint.c:
https://review.coreboot.org/c/coreboot/+/76689/comment/b1423225_839877e5 : PS10, Line 17: write32((void *)(FU740_CLINT + 4 * (uintptr_t)hartid), !!val);
use write32p?
I am not a fan of hiding the type casts.
File src/soc/sifive/fu740/gpio.c:
https://review.coreboot.org/c/coreboot/+/76689/comment/764c41bc_b6bd4aea : PS10, Line 33: uint32_t output_val = read32((void *)SIFIVE_GPIO_OUTPUT_VAL);
use read32p/write32p?
same as above
File src/soc/sifive/fu740/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/76689/comment/7d9eba60_a6ef9014 : PS10, Line 22: //REGION(opensbi, FU740_DRAM, 256K, 4K)
comment not needed?
Done
File src/soc/sifive/fu740/spi.c:
https://review.coreboot.org/c/coreboot/+/76689/comment/0f318b08_3a5d7952 : PS10, Line 186: //sckmode.raw_bits = 0;
why is this code commented here? delete it?
I cleaned it up a bit, but the SPI code needs a proper cleanup. For that I need to test all the MSEL configurations though, but I don't have time for that at the moment.