[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb700/bootblock.c: Get rid of pci_locate_device

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62108 )

Change subject: sb/amd/sb700/bootblock.c: Get rid of pci_locate_device
......................................................................

sb/amd/sb700/bootblock.c: Get rid of pci_locate_device

Signed-off-by: Michał Żygowski 
Change-Id: Ifa8450983ac3dc2e375650079eb627591d66c62e
---
M src/southbridge/amd/sb700/bootblock.c
1 file changed, 5 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/62108/1

diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index a7a466a..be64c23 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -127,7 +127,7 @@
    pci_devfn_t dev;

/* P2P Bridge */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
+	dev = PCI_DEV(0, 0x14, 4);

/* Chip Control: Enable subtractive decoding */
    byte = pci_read_config8(dev, 0x40);
@@ -159,8 +159,7 @@
    pci_write_config8(dev, 0x04, byte);

/* LPC controller */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
-
+	dev =  PCI_DEV(0, 0x14, 3);
    byte = pci_read_config8(dev, 0x4A);
    byte &= ~(1 << 5);	/* disable lpc port 80 */
    pci_write_config8(dev, 0x4A, byte);
@@ -173,13 +172,13 @@
    u32 reg32;

/* Enable LPC controller */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
+	dev = PCI_DEV(0, 0x14, 0);
    reg32 = pci_read_config32(dev, 0x64);
    reg32 |= 0x00100000;	/* lpcEnable */
    pci_write_config32(dev, 0x64, reg32);

-	/* Enable port 80 LPC decode in pci function 3 configuration space. */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);
+	/* Enable port 80 LPC decode in LPC device */
+	dev = PCI_DEV(0, 0x14, 3);
    byte = pci_read_config8(dev, 0x4a);
    byte |= 1 << 5;		/* enable port 80 */
    pci_write_config8(dev, 0x4a, byte);