[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#4) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
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soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Signed-off-by: Huayang Duan

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/4