[coreboot-gerrit] [S] Change in coreboot[main]: sb/intel/bd82x6x: Disable unused PCIe root ports

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Patrick Rudolph.

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78226?usp=email )

Change subject: sb/intel/bd82x6x: Disable unused PCIe root ports
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Patch Set 1:

(3 comments)

File src/southbridge/intel/bd82x6x/pch.h:

https://review.coreboot.org/c/coreboot/+/78226/comment/10ff0696_f99e139c :
PS1, Line 86: #define D28Fx_XCAP		0x42
I believe these are offsets into PCI express capability block at 0x40 + PCI_EXP_xxx from pci_def.h?

```
#define PCI_EXP_FLAGS		2	/* Capabilities register */
#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
```

https://review.coreboot.org/c/coreboot/+/78226/comment/7b7823d2_d9db48e7 :
PS1, Line 88: #define D28Fx_LCTL		0x50
```
#define PCI_EXP_LNKCTL		16	/* Link Control */
```

https://review.coreboot.org/c/coreboot/+/78226/comment/2f08936d_edc4553a :
PS1, Line 90: #define D28Fx_SLSTS		0x58
Seems like 0x58 would be CTL, 0x5A and 0x5B status?
```
#define PCI_EXP_SLTCTL		24	/* Slot Control */
#define PCI_EXP_SLTSTA		26	/* Slot Status */
```