[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Initialize thermal configuration

[Julien Viard de Galbert (Code Review)]

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25439

Change subject: soc/intel/denverton_ns: Initialize thermal configuration
......................................................................

soc/intel/denverton_ns: Initialize thermal configuration

Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375
Signed-off-by: Julien Viard de Galbert 
---
M src/soc/intel/denverton_ns/cpu.c
1 file changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/25439/1

diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index 4434964..ede4dae 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -67,6 +67,29 @@
    write_cr4(read_cr4() | CR4_MCE);
 }

+static void configure_thermal_core(void)
+{
+	msr_t msr;
+	struct cpuid_result cpuid_regs;
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_THERM_INTERRUPT, msr);
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo &= (1 << 3);		/* Clear TM enable */
+	cpuid_regs = cpuid(1);
+	if (cpuid_regs.edx & (1 << 29))
+		msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+}
+
 static void denverton_core_init(device_t cpu)
 {
    msr_t msr;
@@ -76,6 +99,9 @@
    /* Clear out pending MCEs */
    dnv_configure_mca();

+	/* Configure Thermal Sensors */
+	configure_thermal_core();
+
    /* Enable Fast Strings */
    msr = rdmsr(IA32_MISC_ENABLE);
    msr.lo |= FAST_STRINGS_ENABLE_BIT;