Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11739
-gerrit
commit 2fe6e8dd907fb0019b41a4e8f2e9d12ca979cb13 Author: Aaron Durbin adurbin@chromium.org Date: Tue Sep 29 14:54:25 2015 -0500
x86: provide common macro for linking early stages
In order to support verstage on x86 one needs to link verstage like romstage since it needs all the cache-as-ram goodies. Therefore, provide a macro that one can invoke that provides the necessary recipes for linking that particular stage in such an environment.
BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados.
Change-Id: I12f4872df09fff6715829de68fc374e230350c2e Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/arch/x86/Makefile.inc | 49 ++++++++++++++++++++++++------------------- src/arch/x86/assembly_entry.S | 37 ++++++++++++++++++++++++++++++++ src/arch/x86/romstage.S | 37 -------------------------------- 3 files changed, 65 insertions(+), 58 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1779099..f16edcd 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -115,27 +115,44 @@ endif endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
############################################################################### -# romstage +# common support for early assembly includes ###############################################################################
-ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) - -romstage-y += memlayout.ld - # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them # into a single generated file. crt0s = $(cpu_incs-y)
-$(objgenerated)/romstage.inc: $$(crt0s) +$(objgenerated)/assembly.inc: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
+define early_x86_stage +# $1 stage name +# $2 oformat +$(1)-y += memlayout.ld # Add the assembly file that pulls in the rest of the dependencies in -# the right order. Make sure the auto generated romstage.inc is a proper +# the right order. Make sure the auto generated assembly.inc is a proper # dependency. -romstage-y += romstage.S -$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc +$(1)-y += assembly_entry.S +$$(obj)/arch/x86/assembly_entry.$(1).o: $(objgenerated)/assembly.inc + +$$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) + @printf " LINK $$(subst $$(obj)/,,$$(@))\n" + $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $$(obj)/arch/x86/memlayout.$(1).ld --oformat $(2) + LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders 2>&1 | \ + grep -v "Empty loadable segment detected" && \ + $$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders | grep -q ""; if [ $$$$? -eq 0 ]; then \ + echo "Forbidden global variables in "$(1)":"; \ + $$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders; false; \ + else true; fi +endef + +############################################################################### +# romstage +############################################################################### + +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
ifneq ($(CONFIG_ROMCC),y)
@@ -180,21 +197,11 @@ endif romstage-libs ?=
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) -romstage-oformat=elf32-i386 +$(eval $(call early_x86_stage,romstage,elf32-i386)) else -romstage-oformat=elf64-x86-64 +$(eval $(call early_x86_stage,romstage,elf64-x86-64)) endif
-$(objcbfs)/romstage.debug: $$(romstage-objs) $$(romstage-libs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(obj)/arch/x86/memlayout.romstage.ld --oformat $(romstage-oformat) - LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \ - grep -v "Empty loadable segment detected" && \ - if [ -n "`$(NM_romstage) $(objcbfs)/romstage_null.offenders 2>/dev/null`" ]; then \ - echo "Forbidden global variables in romstage:"; \ - $(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \ - else true; fi - # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S new file mode 100644 index 0000000..c23d177 --- /dev/null +++ b/src/arch/x86/assembly_entry.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <cpu/x86/fpu_enable.inc> +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * The assembly.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include <generated/assembly.inc> diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S deleted file mode 100644 index b19b954..0000000 --- a/src/arch/x86/romstage.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/32bit/entry32.inc> -#include <cpu/x86/fpu_enable.inc> -#if IS_ENABLED(CONFIG_SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * The romstage.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include <generated/romstage.inc>