[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Kapil Porwal, Arthur Heymans, Lean Sheng Tan, Werner Zeh.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69227 )

Change subject: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC
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Patch Set 2:

(1 comment)

Patchset:

PS2:
> The PMC bar is set up in booblock/pch.c for these SoCs (meteorlkae seems to have it in soc_die.c) and here PWRMBASE is used (whihc is 0x10 so matching the BAR0 define).
> Should we synchronize these two defines to stay consistent? So either use PWRMBASE in this patch or push another one to fix it in pch.c. 
> WDYT?

Thanks for the suggestion.