[coreboot-gerrit] [XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum

[Bill XIE (Code Review)]

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78906?usp=email )

Change subject: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum
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drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum

Proposed in the comment of commit 29030d0f3dad
(drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume),
during sanitize_cmos(), only reset CMOS range covered by checksum, and
the checksum itself from the file cmos.default in CBFS, in order to
prevent other runtime data in CMOS (e.g. the DRAM training data on
GM45 platforms for s3 resume) being erased.

Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig:
    Bring HEAP_SIZE to a common, large value"), which is already
    before my commit 29030d0f3dad , Thinkpad X200 with
    CONFIG(STATIC_OPTION_TABLE) can resume from s3 again,
    indicating that DRAM training data are no longer erased.

Signed-off-by: Bill XIE 
Co-authored-by: Jonathon Hall 
Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a
---
M src/drivers/pc80/rtc/option.c
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78906/1

diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
index 0954335..5ca44e8 100644
--- a/src/drivers/pc80/rtc/option.c
+++ b/src/drivers/pc80/rtc/option.c
@@ -213,9 +213,10 @@
    		return;

u8 control_state = cmos_disable_rtc();
-		/* Max length of 256 spans bank 0 and bank 1 */
-		for (i = 14; i < MIN(256, length); i++)
+		/* Copy checked range and the checksum from the default */
+		for (i = LB_CKS_RANGE_START; i < MIN(LB_CKS_RANGE_END, length); i++)
    		cmos_write_inner(cmos_default[i], i);
+		cmos_write_inner(cmos_default[LB_CKS_LOC], LB_CKS_LOC);
    	cmos_restore_rtc(control_state);
    }
 }