Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email )
Change subject: src/include/cpu/x86: Add Extended Feature Enable Register Macro ......................................................................
src/include/cpu/x86: Add Extended Feature Enable Register Macro
Details: - Add (POWER_CTL) – Offset 1fc required bits. - Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 1b2 required bits
Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- M src/include/cpu/x86/msr.h 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84174/1
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d369972..30125c4 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -48,6 +48,7 @@ #define IA32_THERM_INTERRUPT 0x19b #define IA32_MISC_ENABLE 0x1a0 #define FAST_STRINGS_ENABLE_BIT (1 << 0) +#define TM1_TM2_EMTTM_ENABLE_BIT (1 << 3) #define SPEED_STEP_ENABLE_BIT (1 << 16) #define IA32_ENERGY_PERF_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -55,10 +56,14 @@ #define ENERGY_POLICY_POWERSAVE 15 #define ENERGY_POLICY_MASK 0xf #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 +#define CRITICAL_TEMP_INTERRUPT_ENABLE (1 << 4) #define SMRR_PHYSBASE_MSR 0x1F2 #define SMRR_PHYSMASK_MSR 0x1F3 #define IA32_PLATFORM_DCA_CAP 0x1f8 #define DCA_TYPE0_EN (1 << 0) +#define ENABLE_BIDIR_PROCHOT (1 << 0) +#define PWR_PERF_PLTFRM_OVR (1 << 18) +#define VR_THERM_ALERT_DISABLE_LOCK (1 << 23) #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 #define IA32_MC_CTL(bank) (IA32_MC0_CTL + 4 * (bank))