Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37349 )
Change subject: AGESA,binaryPI: Remove redundant SSE enable ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37349/1/src/drivers/amd/agesa/cache... File src/drivers/amd/agesa/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/37349/1/src/drivers/amd/agesa/cache... PS1, Line 39: /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
We need to double-check what the alternative does. […]
See arch/x86/bootblock_romcc.S If CONFIG_SSE is selected, SSE is enabled with drivers/cpu/x86/sse_enable.inc The difference here is that the exceptions are not enabled (bit 10).