[coreboot-gerrit] Change in coreboot[master]: [WIP] soc/intel/denverton: Handle MMCONF_BASE_ADDRESS

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50665 )

Change subject: [WIP] soc/intel/denverton: Handle MMCONF_BASE_ADDRESS
......................................................................

[WIP] soc/intel/denverton: Handle MMCONF_BASE_ADDRESS

Add MMCONF_BUS_NUMBER=256, just a guess.

Change-Id: I01309638a9f4ada71e5e3789db34892ed4abfa3b
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/bootblock/bootblock.c
2 files changed, 37 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/50665/1

diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index 569e61d..921cbc9 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -83,19 +83,10 @@

unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	u32 pciexbar_reg;
-	int max_buses;
-
-	pciexbar_reg = get_pciebase();
-	max_buses = get_pcielength();
-
-	if (!pciexbar_reg)
-		return current;
-
-	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-					     pciexbar_reg, 0x0, 0x0,
-					     (u8)(max_buses - 1));
-
+	/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
+	current += acpi_create_mcfg_mmconfig((void *)current,
+					     CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
+					     CONFIG_MMCONF_BUS_NUMBER - 1);
    return current;
 }

diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index 76db62e..b40eecf 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

+#include <assert.h>
 #include <bootblock_common.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <FsptUpd.h>
 #include <intelblocks/fast_spi.h>
 #include <soc/bootblock.h>
-#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
 #include <spi-generic.h>
+#include <stdint.h>
 #include <console/console.h>

const FSPT_UPD temp_ram_init_params = {
@@ -48,6 +52,32 @@
    bootblock_main_with_basetime(base_timestamp);
 };

+static void sanity_check_pci_mmconf(void)
+{
+	u32 pciexbar, base = 0, length = 0;
+
+	pciexbar = pci_s_read_config32(PCH_SA_DEV, PCIEXBAR);
+	assert(pciexbar & (1 << 0));
+
+	switch (pciexbar & MASK_PCIEXBAR_LENGTH) {
+	case MASK_PCIEXBAR_LENGTH_256M:
+		base = pciexbar & MASK_PCIEXBAR_256M;
+		length = 256;
+		break;
+	case MASK_PCIEXBAR_LENGTH_128M:
+		base = pciexbar & MASK_PCIEXBAR_128M;
+		length = 128;
+		break;
+	case MASK_PCIEXBAR_LENGTH_64M:
+		base = pciexbar & MASK_PCIEXBAR_64M;
+		length = 64;
+		break;
+	}
+
+	assert(base == CONFIG_MMCONF_BASE_ADDRESS);
+	assert(length == CONFIG_MMCONF_BUS_NUMBER);
+}
+
 void bootblock_soc_early_init(void)
 {

@@ -58,6 +88,8 @@

void bootblock_soc_init(void)
 {
+	sanity_check_pci_mmconf();
+
    if (CONFIG(BOOTBLOCK_CONSOLE))
    	printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
 };