[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: FSP UPD update

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32026 )

Change subject: soc/intel/cannonlake: FSP UPD update
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
PS1, Line 169: PchPmSlpS0VmRuntimeControl
> As far as I know voltage margining is only used for debug/validation purposes. […]

Isn't this dependent on the mainboard design? i.e. is the board designed to support voltage margining in S0ix? And so it will have an end user impact in terms of power consumption in S0ix? I am curious to understand why this is only a debug/validation thing?