Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23754
Change subject: soc/cavium: Only enable CAR if DRAM PLL isn't running ......................................................................
soc/cavium: Only enable CAR if DRAM PLL isn't running
Change-Id: I76f1a44c215f933af74f4d659de59013f2677dad --- M src/soc/cavium/cn81xx/bootblock.c M src/soc/cavium/cn81xx/bootblock_custom.S 2 files changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/23754/1
diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.c index ea83369..9517fb7 100644 --- a/src/soc/cavium/cn81xx/bootblock.c +++ b/src/soc/cavium/cn81xx/bootblock.c @@ -26,19 +26,6 @@ #include <program_loading.h> #include <timestamp.h>
-static int is_dram_enabled(void) -{ -#if 0 - BDK_CSR_INIT(lmcx_ddr_pll_ctl, node, BDK_LMCX_DDR_PLL_CTL(0)); - if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX)) - return lmcx_ddr_pll_ctl.cn83xx.reset_n; - else - return !lmcx_ddr_pll_ctl.cn9.pll_reset; -#endif - /* FIXME: stub - see __bdk_is_dram_enabled for reference code */ - return 0; -} - static void init_sysreg(void) { #if 0 @@ -105,9 +92,6 @@
void bootblock_soc_early_init(void) { - /* Only lock L2 if DDR3 isn't initialized */ - if (is_dram_enabled()) - return;
/* FIXME: will cache_sync_instructions() do? */ //cache_sync_instructions(); diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S index d3eae1d..00a6aff 100644 --- a/src/soc/cavium/cn81xx/bootblock_custom.S +++ b/src/soc/cavium/cn81xx/bootblock_custom.S @@ -50,6 +50,22 @@ #error Unknown endianness #endif
+ #define BDK_LMCX 0x87e088000000ULL + #define DDR_PLL_CTL0 0x258 + mov x0, (BDK_LMCX >> 32) + lsl x0, x0, 32 + mov x1, (BDK_LMCX & 0xffffffff) + orr x0, x0, x1 + + /* Test if DRAM PLL is running */ + ldr x1, [x0, DDR_PLL_CTL0] + + tst x1, 0x80 + #undef BDK_LMCX + #undef DDR_PLL_CTL0 + + b.ne cache_setup_done + bl _setup_car
cache_setup_done: