[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Fine tune SD card D3 cold timing

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32552 )

Change subject: mb/google/sarien: Fine tune SD card D3 cold timing
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/32552/1/src/mainboard/google/sarien/variants... 
File src/mainboard/google/sarien/variants/sarien/gpio.c:

https://review.coreboot.org/#/c/32552/1/src/mainboard/google/sarien/variants... 
PS1, Line 244: PAD_CFG_GPO(GPP_H12, 1, DEEP),
> It is odd to set this twice in the same table, the timing is not going to be very long and it could  […]

This is modify by Lance. I am not sure what the result if put after. I have tried that as well. Since factory is building, maybe we can try after? Currently order is 1ms, if I put into regular table it increased to 300ms or 200ms I forgot. We can ask Intel it okay or not.