Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )
Change subject: arch/x86: Cache the TSEG region at the top of ram ......................................................................
Patch Set 5:
I have analysis the boot average time, here is my observation
- Average boot time with POSTCAR_STAGE=y is ~815ms (with 1100:finished vboot kernel verification." value ~147ms)
All references by commit hash also please. We will find the source from that.
- Average boot time with POSTCAR_STAGE=n is ~811ms (with 1100:finished vboot kernel verification." value ~137ms)
So its consistent that end of end, we will save ~4ms for sure.
Try to explain the case of 1100 being slower with #1. 4ms of 800ms is 0.5% saving?
Now the benefit of stage_cache_add() is to minimize S3 resume time. On these devices where we are running POC are with S0ix default enable hence we are not even running S3 to utilizes this stage_cache benefits, IMHO, we should add a check based on s0ix_enable chip.h config option to add stage_cache_add entries and don't add into stage_cache if S0ix is enable by mainboard.
I would prefer to make HAVE_ACPI_RESUME a user selectable option in menuconfig. Don't select it and stage cache will remain disabled. We can have devicetree config to override S3 support off.