[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add ability to disable Heci1

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32992 )

Change subject: soc/intel/cannonlake: Add ability to disable Heci1
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Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/32992/5/src/soc/intel/cannonlake/chip.h 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/#/c/32992/5/src/soc/intel/cannonlake/chip.h@424 
PS5, Line 424: Heci1Disabled
make use of config HeciEnabled line 218

https://review.coreboot.org/#/c/32992/5/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32992/5/src/soc/intel/cannonlake/fsp_params.... 
PS5, Line 344: Heci1Disabled
i guess you can use !config->HeciEnabled to assign FSP UPD, in that way you don't need another one