Attention is currently required from: Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47336 )
Change subject: soc/intel/elkhartlake: Add Initial support for Intel PSE ......................................................................
Patch Set 1:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47336/comment/3ba5b94a_79b20bae PS1, Line 2: Tan, Lean Sheng Please use *Lean Sheng Tan*.
https://review.coreboot.org/c/coreboot/+/47336/comment/9fe9e422_b4483725 PS1, Line 11: low-DMIPS computing What does that mean?
https://review.coreboot.org/c/coreboot/+/47336/comment/3028c5d4_de2647a6 PS1, Line 15: add adds
https://review.coreboot.org/c/coreboot/+/47336/comment/5b8d3674_05a13ef7 PS1, Line 15: This patch add initial PSE loading support for EHL. Please describe the coreboot integration in detail. It looks like it’s implemented by loading a blob. What does the blob do? Where will the blob be published? Why is a blob needed at all?
https://review.coreboot.org/c/coreboot/+/47336/comment/1c57260d_243cb3fd PS1, Line 16: 1. Tested how? 2. Please add a reference to the specification.
File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/47336/comment/d3fae5c3_59cfbda0 PS1, Line 200: PSE Please spell it out once in the help text.