[coreboot-gerrit] Change in ...coreboot[master]: riscv: fix bug of riscv

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29767

Change subject: riscv: fix bug of riscv
......................................................................

riscv: fix bug of riscv

The GPT version must be "00 00 01 00" and the small end should be
represented as 0x10000.

Please refer to: https://en.wikipedia.org/wiki/GUID_Partition_Table

Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031
Signed-off-by: Xiang Wang 
---
M util/riscv/sifive-gpt.py
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29767/1

diff --git a/util/riscv/sifive-gpt.py b/util/riscv/sifive-gpt.py
index 7f522d9..f1e4fa8 100755
--- a/util/riscv/sifive-gpt.py
+++ b/util/riscv/sifive-gpt.py
@@ -88,7 +88,7 @@
     def pack_with_crc(self, crc):
         header_size = 92
         header = struct.pack('<8sIIIIQQQQ16sQIII',
-                b'EFI PART', 0x100, header_size, crc, 0,
+                b'EFI PART', 0x10000, header_size, crc, 0,
                 self.current_lba, self.backup_lba, self.first_usable_lba,
                 self.last_usable_lba, self.uniq.get_bytes(),
                 self.part_entries_lba, self.part_entries_number,