Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37865 )
Change subject: mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0 ......................................................................
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So I guess I'm misunderstanding something. Does the kernel treat "opportunistic" S0ix differently from other entries into S0ix? And so that's why this is needed?
The LPIT document https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.... doesn't say anything about this, and just says that the OSPM will call the _DSM function with 5 or 6 as the argument upon entering/exiting the S0 Idle state.
I guess that is true for regular S0ix entry and exit but not for runtme S0ix where you just left system idle and it enters into S0ix. In Runtime S0ix, those _DSM won't get called.
Subrata is correct. for opportunistic/runtime s0ix, it won't call the _DSM and that's why we are having issue w/ PchPmSlpS0Vm075VSupport set thanks
Gotcha.
Anyone have any better ideas? I'm not coming up with much.
my best bet would be inside GFX _PS0/_PS3 because of last device entering into D3 in runtime idle and other cases. I do remember about many W/A place inside my windows days in ASL specifically either storage or GFX side _PS0/_PS3
Also we have noted the power saving is also huge with and without this CL, this might be useful for devices with lower battery capacity
I don't see any PS3, PS0 in current GFX acpi device. I will try put some log in GFX, SPI PS0/PS3 and compare in btwn.