[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp: Add USE_COREBOOT_SPECIFIC_FSP_HEADERS

[Shuo Liu (Code Review)]

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81039?usp=email )

Change subject: soc/intel/xeon_sp: Add USE_COREBOOT_SPECIFIC_FSP_HEADERS
......................................................................

soc/intel/xeon_sp: Add USE_COREBOOT_SPECIFIC_FSP_HEADERS

For SKX to SPR, there are 2 class of FSP headers. One class is
common headers, like <IioUniversalDataHob.h> which is commonly
used for all bootloaders, include UEFI and SlimBoot. Another class
is coreboot extended FSP headers, like <hob_iiouds.h>. These
extended headers are used in coreboot only and maintained in
coreboot repo.

In GNR and future generations, the generality of FSP headers is
improved and these extended headers are not needed. Hence files
like <hob_iiouds.h> will not be used. Accordingly, we need to
remove the references of these headers from Xeon-SP common codes
conditionally.

Change-Id: Iefd45e8e0518e88529ae3edcdd8ed08a49f0e475
Signed-off-by: Shuo Liu 
---
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/skx/Kconfig
M src/soc/intel/xeon_sp/spr/Kconfig
6 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/81039/1

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 18474ec..15d129a 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -107,4 +107,7 @@
 config HAVE_IOAT_DOMAINS
    bool

+config USE_COREBOOT_SPECIFIC_FSP_HEADERS
+	bool
+
 endif ## SOC_INTEL_XEON_SP
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index ac166c3..1e89f21 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -7,6 +7,7 @@
    select CACHE_MRC_SETTINGS
    select NO_FSP_TEMP_RAM_EXIT
    select HAVE_INTEL_FSP_REPO
+	select USE_COREBOOT_SPECIFIC_FSP_HEADERS
    help
      Intel Cooper Lake-SP support

diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h
index 3727777..847d95a 100644
--- a/src/soc/intel/xeon_sp/include/soc/chip_common.h
+++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h
@@ -3,7 +3,9 @@
 #ifndef _CHIP_COMMON_H_
 #define _CHIP_COMMON_H_

+#if CONFIG(USE_COREBOOT_SPECIFIC_FSP_HEADERS)
 #include <hob_iiouds.h>
+#endif

union xeon_domain_path {
    unsigned int domain_path;
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h
index a7d5dac..b881cb4 100644
--- a/src/soc/intel/xeon_sp/include/soc/util.h
+++ b/src/soc/intel/xeon_sp/include/soc/util.h
@@ -4,7 +4,9 @@
 #define _XEON_SP_SOC_UTIL_H_

#include <cpu/x86/msr.h>
+#if CONFIG(USE_COREBOOT_SPECIFIC_FSP_HEADERS)
 #include <hob_iiouds.h>
+#endif

#define MEM_ADDR_64MB_SHIFT_BITS 26

diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
index 5d84387..52f4e62 100644
--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
@@ -5,6 +5,7 @@
    select XEON_SP_COMMON_BASE
    select PLATFORM_USES_FSP2_0
    select NO_FSP_TEMP_RAM_EXIT
+	select USE_COREBOOT_SPECIFIC_FSP_HEADERS
    help
      Intel Skylake-SP support

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index bb88bec..ce170ad 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -13,6 +13,7 @@
    select SOC_INTEL_CSE_SERVER_SKU
    select XEON_SP_COMMON_BASE
    select HAVE_IOAT_DOMAINS
+	select USE_COREBOOT_SPECIFIC_FSP_HEADERS
    help
      Intel Sapphire Rapids-SP support