[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
PS5, Line 177: 	enable_ramstage_caching(top_of_ram, top_of_ram_size);
> > Do we want to add this as an option to postcar api?
>
> that should be ideal but how do we know which MTRR is runtime MTRR and need to program before loading postcar stage? Because when control reaches postcar, inside postcar_frame we have multiple MTRR base and size, there is no such order to tell that index[0] is the one what i have to set before loading posrcar.

Aaron, do you mean call set_var_mtrr(base, size)  from postcar_frame_add_mtrr() function itself so all soc can leverage this benefit without dedicated soc code change ?