[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: acpi_wake_source()

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49356 )

Change subject: soc/intel/broadwell: acpi_wake_source()
......................................................................

soc/intel/broadwell: acpi_wake_source()

Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/baytrail/ramstage.c
M src/soc/intel/broadwell/ramstage.c
2 files changed, 11 insertions(+), 22 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/49356/1

diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index e199e9f..f2c9cdc 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -117,12 +117,13 @@
 }

/* Save bit index for first enabled event in PM1_STS for _SB._SWS */
-static void s3_save_acpi_wake_source(struct global_nvs *gnvs)
+static void s3_save_acpi_wake_source(void)
 {
    struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+	struct global_nvs *gnvs = acpi_get_gnvs();
    uint16_t pm1;

-	if (!ps)
+	if (!ps || !gnvs)
    	return;

pm1 = ps->pm1_sts & ps->pm1_en;
@@ -142,14 +143,6 @@
           gnvs->pm1i);
 }

-static void s3_resume_prepare(void)
-{
-	struct global_nvs *gnvs = acpi_get_gnvs();
-
-	if (gnvs && acpi_is_wakeup_s3())
-		s3_save_acpi_wake_source(gnvs);
-}
-
 static void baytrail_enable_2x_refresh_rate(void)
 {
    u32 reg;
@@ -172,7 +165,8 @@
    write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);

/* Indicate S3 resume to rest of ramstage. */
-	s3_resume_prepare();
+	if (acpi_is_wakeup_s3())
+		s3_save_acpi_wake_source();

/* Run reference code. */
    baytrail_run_reference_code();
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index b4f38a5..2e50555 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -12,13 +12,14 @@
 #include <soc/intel/broadwell/chip.h>

/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
-static void save_acpi_wake_source(struct global_nvs *gnvs)
+static void save_acpi_wake_source(void)
 {
    struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+	struct global_nvs *gnvs = acpi_get_gnvs();
    uint16_t pm1;
    int gpe_reg;

-	if (!ps)
+	if (!ps || !gnvs)
    	return;

pm1 = ps->pm1_sts & ps->pm1_en;
@@ -62,16 +63,10 @@
           gnvs->pm1i, gnvs->gpei);
 }

-static void s3_resume_prepare(void)
-{
-	struct global_nvs *gnvs = acpi_get_gnvs();
-
-	if (gnvs && acpi_is_wakeup_s3())
-		save_acpi_wake_source(gnvs);
-}
-
 void broadwell_init_pre_device(void *chip_info)
 {
-	s3_resume_prepare();
+	if (acpi_is_wakeup_s3())
+		save_acpi_wake_source();
+
    broadwell_run_reference_code();
 }