[coreboot-gerrit] Change in coreboot[master]: intel/i945,i82801gx: Refactor early PCI bridge reset

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )

Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... 
File src/northbridge/intel/i945/early_init.c:

https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... 
PS1, Line 876: mdelay(200);
> We built the i945 code for secunet devices, some of which come with an FPGA card (that, indeed, impl […]

If we'd rebase that platform ever on master again, we'd have to validate
all that again, anyway. So please just remove it.

I also doubt very much that this was ever intended. I guess somebody
confused the delay *after* the reset until devices have to show up with
the assertion interval? Now, I don't know PCI that well, if the reset
is edge and not level triggered, it wouldn't make a difference.

In the long run, the allocator should be made aware of reset times and
ensure that downstream devices get the necessary time to show up, I guess.