Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45389 )
Change subject: nb/intel/x4x: Clean up TPM-related code ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45389/4/src/northbridge/intel/x4x/b... File src/northbridge/intel/x4x/bootblock.c:
https://review.coreboot.org/c/coreboot/+/45389/4/src/northbridge/intel/x4x/b... PS4, Line 12: /* Disable LaGrande Technology (LT) */
that's just plain wrong.
From reference code itself:
_prepareToCallMemRefCode: ; Perform read to TPM public space to identify non-LT platform to MCH mov esi, 0FED40000h mov eax, fs:[esi]
If anything, I can change things in CB:45390
https://review.coreboot.org/c/coreboot/+/45389/4/src/northbridge/intel/x4x/b... PS4, Line 13: reg32 = TPM32(0);
you want to wait for the TPM_ACCESS_VALID bit set, so this code is again very wrong.
I think none of the supported x4x boards has a TXT-capable MCH. I have an HP machine with a TXT-capable MCH, so I could try to see what happens there. It's not currently with me, though.