Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33624 )
Change subject: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/acpi/cpu.asl File src/soc/amd/stoneyridge/acpi/cpu.asl:
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/acpi/cpu.asl... PS3, Line 37: If (LGreaterEqual (\PCNT, 8))
I kind of thought 2 CUs, i.e. 4 cores was the max for Models 60-6F. […]
I'll have to double check, but when I used the original BIOS and booted to windows, there were some indication of 4 cores making 8 processing units (hyperthread ?)
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/northbridge.... File src/soc/amd/stoneyridge/northbridge.c:
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/northbridge.... PS3, Line 358: .devices = pci_device_ids, I noticed I missed, uploaded a patch 4, but for some unknown reason it did not show up here. I decided to wait, just in case it would come up later... apparently did not. Will resubmit.