[coreboot-gerrit] Change in coreboot[master]: soc/mediatek: Fill coreboot table with PCIe info

[Jianjun Wang (Code Review)]

Attention is currently required from: Hung-Te Lin.
Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63252

to look at the new patch set (#4).

Change subject: soc/mediatek: Fill coreboot table with PCIe info
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soc/mediatek: Fill coreboot table with PCIe info

In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang 
Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406
---
M src/soc/mediatek/common/pcie.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63252/4