[coreboot-gerrit] Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization
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Patch Set 14:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37168/14/src/southbridge/amd/agesa/... 
File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/14/src/southbridge/amd/agesa/... 
PS14, Line 102: 	tmp =  DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 
trailing whitespace

https://review.coreboot.org/c/coreboot/+/37168/14/src/southbridge/amd/pi/hud... 
File src/southbridge/amd/pi/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/14/src/southbridge/amd/pi/hud... 
PS14, Line 135: 	tmp =  DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 
trailing whitespace