[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable MrcSafeConfig

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40106 )

Change subject: soc/intel/tigerlake: Disable MrcSafeConfig
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soc/intel/tigerlake: Disable MrcSafeConfig

This change disables MrcSafeConfig option during MRC training.
FSP 2527 and later versions support running MRC without this
option hence disabling it.

BUG=b:150357377
BRANCH=master
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269
---
M src/soc/intel/tigerlake/meminit.c
1 file changed, 0 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/40106/1

diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c
index 864f079..ec7aed7 100644
--- a/src/soc/intel/tigerlake/meminit.c
+++ b/src/soc/intel/tigerlake/meminit.c
@@ -231,7 +231,6 @@
    /* LPDDR4x does not allow interleaved memory */
    mem_cfg->DqPinsInterleaved = 0;
    mem_cfg->ECT = board_cfg->ect;
-	mem_cfg->MrcSafeConfig = 0x1;

read_md_spd(info, &spd_data, &spd_len);
    mem_cfg->MemorySpdDataLen = spd_len;