[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 11:
> Yes, this was written with tongue in the cheek. Give us native raminit and source, and we'll likely throw out any UEFI and instantly take away 50+ ms from cold boots. Unless the figures against a solution with POSTCAR_STAGE=y show a much more significant improvement (4 ms of 830ms is <0.5 %) I see no value in the approach of skipping the separate POSTCAR_STAGE.

Its not only size reduction as i have pointed out in past gerrit update. Coreboot should have flexible stage requirement, where one should be able to pick or drop a stage. if could see the note from Aaron, why he has introduced postcar and we should be able to achieve the say in ramstage as well without introducing a new stage if we wish.