[coreboot-gerrit] [S] Change in coreboot[master]: sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69878 )

Change subject: sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros
......................................................................

sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros

Change-Id: Id281a3478051c4876ccbe26452d8744769c86654
Signed-off-by: Elyes Haouas 
---
M src/southbridge/intel/i82801gx/early_init.c
M src/southbridge/intel/i82801gx/i82801gx.h
M src/southbridge/intel/i82801gx/lpc.c
3 files changed, 17 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69878/1

diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index deb3deb..dda5c00 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -6,6 +6,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/rcba.h>
+#include <southbridge/intel/common/tco.h>

#include "chip.h"
 #include "i82801gx.h"
@@ -57,8 +58,6 @@
    pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN);
 }

-#define TCO_BASE 0x60
-
 #if ENV_RAMINIT
 void i82801gx_early_init(void)
 {
@@ -72,9 +71,9 @@

printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
    RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	write_pmbase16(TCO_BASE + 0x8, (1 << 11));	/* halt timer */
-	write_pmbase16(TCO_BASE + 0x4, (1 << 3));	/* clear timeout */
-	write_pmbase16(TCO_BASE + 0x6, (1 << 1));	/* clear 2nd timeout */
+	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT);
+	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
+	write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
    printk(BIOS_DEBUG, " done.\n");

/* program secondary mlt XXX byte? */
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 68a32df..cf76a40 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -320,7 +320,6 @@
 #define DEVACT_STS	0x44
 #define SS_CNT		0x50
 #define C3_RES		0x54
-#define TCO1_CNT	0x68

#endif /* __ACPI__ */
 #endif				/* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index ec0df27..5dcae42 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -20,6 +20,7 @@
 #include <southbridge/intel/common/hpet.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/spi.h>
+#include <southbridge/intel/common/tco.h>

#include "chip.h"
 #include "i82801gx.h"
@@ -440,9 +441,9 @@
    pci_or_config16(dev, GEN_PMCON_1, 1 << 4);

/* TCO_Lock */
-	tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT);
+	tco1_cnt = inw(DEFAULT_PMBASE + PMBASE_TCO_OFFSET + TCO1_CNT);
    tco1_cnt |= (1 << 12); /* TCO lock */
-	outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT);
+	outw(tco1_cnt, DEFAULT_PMBASE + PMBASE_TCO_OFFSET + TCO1_CNT);

/* Indicate finalize step with post code */
    outb(POST_OS_BOOT, 0x80);