[coreboot-gerrit] Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM

[Michael Niewöhner (Code Review)]

Hello  Felix Singer, Lijian Zhao, John Su, Anil Kumar K, build bot (Jenkins), David Wu, Patrick Georgi, Maulik V Vaghela, Matt DeVillier, Ravishankar Sarawadi, Alex Levin, Paul Menzel, Andrey Petrov, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, Nico Huber, Caveh Jalali, Christian Walter, Andrey Petrov, Edward O'Callaghan, Tim Chen, EricR Lai, Jonas Löffelholz, Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Jeremy Soller, Thomas Heijligen, Subrata Banik, Aamir Bohra, Paul Fagerburg, Andrew McRae, Elyes HAOUAS, Tim Wawrzynczak, Nick Vaccaro, Thejaswani Putta,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45417

to look at the new patch set (#2).

Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
......................................................................

soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM

C6DRAM is not board design specific, so remove it from devicetree
config. Instead, enable it on supported platforms.

From Intel doc# 615211-005:
The C6DRAM feature saves the processor internal state at Package C6 and
deeper to DRAM instead of on-die SRAM. When the processor state has been
saved to DRAM, the dedicated save/restore SRAM modules are power gated,
enabling idle power savings.

This power gating feature - to my knowlege - doesn't depend on board
design, thus shouldn't cause any issues. Hopefully.

Boards that need testing / have been tested:

[]  google/dedede
[]  google/deltaur
[]  google/drallion
[]  google/hatch
[]  google/sarien
[]  google/volteer
[]  intel/cannonlake_rvp
[]  intel/coffeelake_rvp
[]  intel/jasperlake_rvp
[]  intel/tglrvp
[]  prodrive/hermes
[]  purism/librem_whl
[x] system76/lemp9

Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/romstage/fsp_params.c
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
8 files changed, 3 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45417/2