[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update DPTC setting for SMT

[Paul Menzel (Code Review)]

Attention is currently required from: Jason Nien, EricKY Cheng, Isaac Lee, Martin Roth, Tim Van Patten, Eric Peers, Karthikeyan Ramasubramanian.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69830 )

Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for SMT
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Patch Set 3:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69830/comment/1824e401_260ff402 
PS3, Line 11: enable
enabled

https://review.coreboot.org/c/coreboot/+/69830/comment/a7e03fee_57829f47 
PS3, Line 11: configurations on devicetree would be 0 when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document #57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA and vrm_soc_current_limit_mA on devicetree with thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoid any thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A.
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