[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brox: Include CSE reset in mainboard reset expectation

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85642?usp=email )

Change subject: mb/google/brox: Include CSE reset in mainboard reset expectation
......................................................................

mb/google/brox: Include CSE reset in mainboard reset expectation

If CSE is in RO, then a reset is expected for CSE to jump to RW. Include
that reset in mainboard_expects_another_reset() logic. This will avoid
unnecessary warm reset during regular boot flow in boards with non-UFS
storage.

BUG=None
TEST=Build Brox BIOS image and boot to OS. Ensure that redundant reset
to disable UFS controller is avoided.
Before this change:
[INFO ]  Disabling UFS controllers
[INFO ]  Warm Reset after disabling UFS controllers
[INFO ]  system_reset() called!
<snip>
[DEBUG]  HECI: Global Reset(Type:1) Command
<snip>
[INFO ]  Disabling UFS controllers
[INFO ]  Warm Reset after disabling UFS controllers
[INFO ]  system_reset() called!

After this change:
[DEBUG]  HECI: Global Reset(Type:1) Command
<snip>
[INFO ]  Disabling UFS controllers
[INFO ]  Warm Reset after disabling UFS controllers
[INFO ]  system_reset() called!

Change-Id: I80a46b15813b6bdfa6c029c54590f4b7c2a6754b
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85642
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/mainboard/google/brox/variants/baseboard/brox/romstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
index 66ed99b..6a03a9a 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
@@ -3,6 +3,7 @@
 #include <baseboard/variants.h>
 #include <cbfs.h>
 #include <ec/google/chromeec/ec.h>
+#include <intelblocks/cse.h>
 #include <security/vboot/vboot_common.h>
 #include <security/vboot/misc.h>
 #include <soc/romstage.h>
@@ -53,9 +54,14 @@

bool mainboard_expects_another_reset(void)
 {
+	/* Do not change the order of the check in this function */
    if (vboot_recovery_mode_enabled())
    	return false;

+	/* If CSE is booting from RO, CSE state switch will issue a reset anyway. */
+	if (!is_cse_boot_to_rw())
+		return true;
+
    if (!CONFIG(VBOOT) ||
        (vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC) &&
        vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_AUXFW_SOFTWARE_SYNC)))