Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82637?usp=email )
Change subject: mb/google/brya/variants/trulo: Support OCP fault on A0/1 ports ......................................................................
mb/google/brya/variants/trulo: Support OCP fault on A0/1 ports
The devicetree entry and gpio.c updated to map the OC fault signal from A0/A1 ports in Trulo.
BUG=b:335838378 TEST= NA
Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a --- M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb M src/mainboard/google/brya/variants/trulo/gpio.c 2 files changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/82637/1
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb index a5e2217..c6ef3b3 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb @@ -1,4 +1,8 @@ chip soc/intel/alderlake + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + device domain 0 on end end diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c index beee6fc..1a6d1b1 100644 --- a/src/mainboard/google/brya/variants/trulo/gpio.c +++ b/src/mainboard/google/brya/variants/trulo/gpio.c @@ -8,7 +8,10 @@
/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* TODO */ + /* A14 : USB_OC1# ==> USB_A0_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A14, NONE, NF1, LOCK_CONFIG), + /* A15 : USB_OC2# ==> USB_A1_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A15, NONE, NF1, LOCK_CONFIG), };
/* Early pad configuration in bootblock */