[coreboot-gerrit] Change in coreboot[master]: riscv: add support for OpenSBI

[Xiang Wang (Code Review)]

Hello ron minnich, Shawn C, Patrick Rudolph, Jonathan Neuschäfer, Philipp Deppenwiese, build bot (Jenkins), Philipp Hug, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32394

to look at the new patch set (#14).

Change subject: riscv: add support for OpenSBI
......................................................................

riscv: add support for OpenSBI

Call OpenSBI in M-Mode and use it to set up SBI and to lockdown the
platform. It will also jump to the specified payload when done.
This behaviour is similar to BL31 on aarch31.

The payload is 41KiB in size on qemu.

Tested on qemu-riscv:
Required to boot a kernel as OpenSBI's instruction emulation feature
is required on that virtual machine.

Tested on SiFive/unleashed:
The earlycon is working. No console after regular serial driver
should take over, which might be related to kernel config.

Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d
Signed-off-by: Xiang Wang 
Signed-off-by: Patrick Rudolph 
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.inc
M src/arch/riscv/boot.c
M src/arch/riscv/include/arch/boot.h
A src/arch/riscv/opensbi.c
M src/arch/riscv/payload.c
M src/arch/riscv/tables.c
7 files changed, 182 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32394/14