Attention is currently required from: Hung-Te Lin, Yu-Ping Wu.
Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85914?usp=email )
Change subject: soc/mediatek/common/dp: Add read/write APIs for DP Phy register ......................................................................
soc/mediatek/common/dp: Add read/write APIs for DP Phy register
MT8196's eDP architecture is different from previous SoCs. DP Phy needs to be configured during the initialization. Add read/write APIs for DP Phy register configuration. Add a mock definition EDP_PHY_BASE for the SoC that do not support DP Phy configuration.
BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-rauru coreboot TEST=check FW screen on Navi
Change-Id: I5c00d0aa7e35f03cc3c3aef6a58eadd3d334d8ed Signed-off-by: Yidi Lin yidilin@chromium.org --- M src/soc/mediatek/common/dp/dptx_common.c M src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h M src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h M src/soc/mediatek/mt8188/include/soc/dptx.h M src/soc/mediatek/mt8195/include/soc/dptx.h 6 files changed, 67 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/85914/1
diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c index 0d078cd..b43bf51 100644 --- a/src/soc/mediatek/common/dp/dptx_common.c +++ b/src/soc/mediatek/common/dp/dptx_common.c @@ -215,6 +215,7 @@ void dptx_init_variable(struct mtk_dp *mtk_dp) { mtk_dp->regs = (void *)EDP_BASE; + mtk_dp->phy_regs = (void *)EDP_PHY_BASE; mtk_dp->train_info.sys_max_linkrate = DP_LINKRATE_HBR3; mtk_dp->train_info.linkrate = DP_LINKRATE_HBR2; mtk_dp->train_info.linklane_count = DP_LANECOUNT_4; diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index a7901e3..e8180e4 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -66,6 +66,64 @@ mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0); }
+u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset) +{ + void *addr = mtk_dp->phy_regs + offset; + + if (!mtk_dp->phy_regs) { + printk(BIOS_ERR, "%s: unsupported API\n", __func__); + return 0; + } + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", + __func__, offset, mtk_dp->regs); + return 0; + } + + return read32(addr); +} + +void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) +{ + void *addr = mtk_dp->phy_regs + offset; + + if (!mtk_dp->phy_regs) { + printk(BIOS_ERR, "%s: unsupported API\n", __func__); + return; + } + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", + __func__, offset, mtk_dp->regs); + return; + } + + write32(addr, val); +} + +void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) +{ + void *addr = mtk_dp->phy_regs + offset; + + if (!mtk_dp->phy_regs) { + printk(BIOS_ERR, "%s: unsupported API\n", __func__); + return; + } + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", + __func__, offset, mtk_dp->regs); + return; + } + + /* + * TODO: modify to clrsetbits32(addr, mask, val); + * There is asserion error when testing assert((val & mask) == val). + */ + clrsetbits32(addr, mask, val & mask); +} + void dptx_hal_verify_clock(struct mtk_dp *mtk_dp) { u32 m, n, ls_clk, pix_clk; diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h index db686d2..1d7e135 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -198,6 +198,7 @@ u32 max_hdisplay; u32 max_vdisplay; void *regs; + void *phy_regs; int disp_status; bool power_on; bool audio_enable; diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index 778fe46..7ed41e8 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -65,6 +65,9 @@ bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, int swing_value, int preemphasis); u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp); +u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset); +void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); +void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset); void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask); void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); diff --git a/src/soc/mediatek/mt8188/include/soc/dptx.h b/src/soc/mediatek/mt8188/include/soc/dptx.h index 71a6ff6..c910bed 100644 --- a/src/soc/mediatek/mt8188/include/soc/dptx.h +++ b/src/soc/mediatek/mt8188/include/soc/dptx.h @@ -5,4 +5,6 @@
#include <soc/dptx_common.h>
+#define EDP_PHY_BASE 0 + #endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx.h b/src/soc/mediatek/mt8195/include/soc/dptx.h index 9af5b14..50b73ae 100644 --- a/src/soc/mediatek/mt8195/include/soc/dptx.h +++ b/src/soc/mediatek/mt8195/include/soc/dptx.h @@ -5,4 +5,6 @@
#include <soc/dptx_common.h>
+#define EDP_PHY_BASE 0 + #endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ */