Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )
Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... PS2, Line 1593: The clock rate should be (data rate/2 - 4), : * and the 4MHz is introduced to reduce interference from : * RF peripherals like modem, WiFi, BlueTooth. can you revise this to
The clock rate is usually (data rate/2 - 4), and the 4MHz is introduced to reduce interference from RF peripherals like modem, WiFi, BlueTooth. For some higher frequency the number may be different.
https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... PS2, Line 1599: 796
I wonder if it'll be more clear if we do […]
Ack
https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... PS2, Line 1608: 1792
the real clock DRAM control using is 796, 1596 and 1792 for avoid other RF device. […]
Ack