[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/mendocino: Increase CBFS_MCACHE size

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Paul Menzel, Jon Murphy, Arthur Heymans, Fred Reitberger.

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69827 )

Change subject: soc/amd/mendocino: Increase CBFS_MCACHE size
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69827/comment/5e0da597_db7adabe 
PS1, Line 11: This reduction along with the available free space in PSP shared buffer
            : (32 KiB)
> > We cannot jump bump the PSP Shared buffer size in coreboot. […]

It does not have to be necessarily a multiple of 2. But it still requires change in PSP. Once PSP verstage completes execution, PSP BL copies the PSP transfer buffer into a separate region in SRAM and then later copies that data from SRAM into DRAM before releasing x86 out of reset. Currently the allocated space for that SRAM copy/backup is 32 KiB. This needs to be updated in PSP. Otherwise the contents in the PSP transfer buffer will be incomplete.