[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Disable Intel PSE by default

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59484 )

Change subject: soc/intel/elkhartlake: Disable Intel PSE by default
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soc/intel/elkhartlake: Disable Intel PSE by default

Disable PSE loading by default. If left enabled (current default),
the EHL coreboot will end up in endless restart loop, due to FSP
unable to locate PSE FW image and trigger global reset.

However disabling this flag (PchPseEnable) will cause the coreboot
to trigger a single reset due to CSE signal (HECI: CSE does not
meet required prerequisites). The reason behind this is that FSP
need to perform static disabling (power gate) to fully shut down
PSE HW, and to do this will need to global reset entire system
including CSE. Then PMC will power gate PSE from the start.

To avoid this behavior, the best way to disable PSE is to disable
via IFWI FIT softstrap (For specific detail can refer to Intel EHL
coreboot MR2 release notes). With this, PMC will power gate PSE
from the first cold boot and system will boot happily without
single reset behavior.

Signed-off-by: Lean Sheng Tan 
Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59484
Tested-by: build bot (Jenkins) 
Reviewed-by: Werner Zeh 
Reviewed-by:  Felix Singer 
---
M src/soc/intel/elkhartlake/romstage/fsp_params.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved
   Felix Singer: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
index a15b030..ecb6304 100644
--- a/src/soc/intel/elkhartlake/romstage/fsp_params.c
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -123,6 +123,8 @@
    			       config->ibecc.region_mask);
    	}
    }
+	/* PSE (Intel Programmable Services Engine) switch */
+	m_cfg->PchPseEnable = 0;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)