Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37950 )
Change subject: src: Remove old romcc comments and workarounds ......................................................................
src: Remove old romcc comments and workarounds
romcc is now gone, so drop all old comments/hacks to work around it.
Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b Signed-off-by: Jacob Garber jgarber1@ualberta.ca --- M src/arch/x86/include/arch/cpu.h M src/console/post.c M src/include/pc80/mc146818rtc.h M src/include/stdint.h M src/lib/program.ld M src/northbridge/intel/gm45/bootblock.c M src/superio/nsc/pc87417/pc87417.h 7 files changed, 28 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/37950/1
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index c8cf8c7..59eb9ad 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -261,7 +261,6 @@ return ci; }
-/* romcc is segfaulting in some cases. */ struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ @@ -281,7 +280,6 @@
}
-/* romcc does not understand regparm. */ #define asmlinkage __attribute__((regparm(0)))
/* diff --git a/src/console/post.c b/src/console/post.c index 8c28ceb..a426fcc 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -82,6 +82,30 @@ } }
+void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); + cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} + #if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value) { diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index afa4d97..ecfa76d 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -223,32 +223,7 @@ #define CMOS_POST_EXTRA_DEV_PATH 0x01
void cmos_post_log(void); - -/* cmos_post_init() is exposed in this manner because it also needs to be called - * by bootblock code compiled by romcc. */ -static inline void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); - cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} +void cmos_post_init(void); #else static inline void cmos_post_log(void) {} static inline void cmos_post_init(void) {} diff --git a/src/include/stdint.h b/src/include/stdint.h index b534add..b3e4cb3 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -14,10 +14,6 @@ #ifndef STDINT_H #define STDINT_H
-/* romcc does not support long long, _Static_assert, or _Bool, so we must ifdef that code out. - Also, GCC can provide its own implementation of stdint.h, so in theory we could use that - instead of this custom file once romcc is no more. */ - /* Fixed width integer types */ typedef signed char int8_t; typedef unsigned char uint8_t; diff --git a/src/lib/program.ld b/src/lib/program.ld index a9d4e48..697ab69 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -27,8 +27,7 @@ _program = .; _text = .; /* - * The .rom.* sections are to acommodate x86 romstage. romcc as well - * as the assembly files put their text and data in these sections. + * The .rom.* sections are to acommodate x86 romstage. */ *(.rom.text); *(.rom.data); diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index dda2b58..58b99ac 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -14,9 +14,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h>
-/* Just re-define these instead of including gm45.h. It blows up romcc. */ -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 +#include "gm45.h"
void bootblock_early_northbridge_init(void) { diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index c3fc5ef..cb6515d 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -31,9 +31,7 @@ #define PC87417_RTC 0x10
#define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO) -/* This is to get around a romcc bug */ -/* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */ -#define PC87417_XBUS_DEV PNP_DEV(0x2e, 0x0f) +#define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS)
#define PC87417_GPSEL 0xf0 #define PC87417_GPCFG1 0xf1