[coreboot-gerrit] Change in coreboot[master]: mb/google/octopus: Disable XHCI LFPS power management by sku for garg

[Kevin Chiu (Code Review)]

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46701 )

Change subject: mb/google/octopus: Disable XHCI LFPS power management by sku for garg
......................................................................

mb/google/octopus: Disable XHCI LFPS power management by sku for garg

LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/octopus/variants/garg/overridetree.cb
M src/mainboard/google/octopus/variants/garg/variant.c
2 files changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/46701/1

diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb
index f3c580d..971d0d8 100644
--- a/src/mainboard/google/octopus/variants/garg/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb
@@ -192,4 +192,5 @@

# Disable compliance mode
    register "DisableComplianceMode" = "1"
+	register "disable_xhci_lfps_pm" = "0"
 end
diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c
index 7c84f26..0a6574d 100644
--- a/src/mainboard/google/octopus/variants/garg/variant.c
+++ b/src/mainboard/google/octopus/variants/garg/variant.c
@@ -8,6 +8,7 @@
 #include <delay.h>
 #include <gpio.h>
 #include <variant/sku.h>
+#include <soc/intel/apollolake/chip.h>

const char *mainboard_vbt_filename(void)
 {
@@ -42,3 +43,21 @@
    	return;
    }
 }
+
+void variant_update_devtree(struct device *dev)
+{
+	struct soc_intel_apollolake_config *cfg = NULL;
+
+	cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
+
+	if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) {
+		switch (google_chromeec_get_board_sku()) {
+		case SKU_17_LTE:
+		case SKU_18_LTE_TS:
+			cfg->disable_xhci_lfps_pm = 1;
+			return;
+		default:
+			return;
+		}
+	}
+}